Memory circuits, such as read-only-memories (ROMS), are ubiquitous in modern computing devices. Efforts continue to achieve increased density, lower power, and better performance. Many current devices use a single transistor to store a single bit of data. There are density limits to such types of designs, as the ROM cell can be designed only as small as is possible within the limits of current manufacturing technology. Various prior art approaches have been plagued by undesirably increased memory access and cycle times, as well as undesirable increases in leakage current and bit line coupling.
U.S. Pat. No. 5,528,534 to Shoji discloses a high-density ROM employing multiple bit line interconnection. Data that would normally be represented by multiple bits of information is effectively stored at a single memory site within a ROM. This is accomplished by employing a multiple bit line memory architecture, in conjunction with a data decoder. With the arrangement disclosed in Shoji, it is possible to store, at a single memory site, information that would have required up to log2(n(n−1)/2)+1 individual memory sites in a conventional ROM (where n is the number of independent bit lines connected to an individual memory element in the invention). The Shoji invention is particularly well suited to what would be considered relatively low-speed data retrieval systems, such as those adapted to provide audio and/or video to a user on a real time basis.
Therefore, techniques for addressing the deficiencies of prior art approaches would be desirable.